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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:19:32 10/13/2009 
-- Design Name: 
-- Module Name:    ir - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Intructions Register
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ir is
    Port ( I : in  STD_LOGIC_VECTOR (31 downto 0);
			  op : out  STD_LOGIC_VECTOR (5 downto 0);
           rs : out  STD_LOGIC_VECTOR (4 downto 0);
           rt : out  STD_LOGIC_VECTOR (4 downto 0);
           rd : out  STD_LOGIC_VECTOR (4 downto 0);
           funct : out  STD_LOGIC_VECTOR (5 downto 0);
           clock : in  STD_LOGIC);
end ir;

architecture Behavioral of ir is

begin
if (clock='1' and clock'event) then
 op <= I(

end Behavioral;

